4 months ago
An exciting opportunity has arisen for a talented Senior or Principal Design Verification Engineer. You will participate in all aspects of digital verification for complete mixed signal IC developments, work on complex verification systems and contribute towards improvements in verification methodology within Cirrus Logic. This is a real chance for you to get heavily involved in cutting edge projects working in a global organisation. This is a real chance for you to get heavily involved in cutting edge projects working in a global organisation focused on innovation. In return, we offer you a great range of benefits including personal and professional development, a uniquely flat culture and much, much more!
* Definition of IC verification strategy for complex mixed signal systems. Encompassing Simulation, Formal Verification and Emulation.
* Leadership of verification teams, including resource planning, task assignment and reporting through to the delivery of thoroughly verified ICs.
* Definition of IC verification plans linking product requirements through to detailed testcases.
* Development of reliable and reusable testbenches for complex subsystems and mixed signal ICs.
* Lead and participate in verification Expert Groups to identify and drive enhancements to the verification process.
* Mentorship and support of other Engineers to develop their skills and improve the verification practices within the team.
* Hands-on project design/verification involvement.
* Collaboration with other Engineering disciplines to maximize efficiency of development activities.
Required Skills and Qualifications
* Degree or equivalent in Electronics/Computer Science or equivalent discipline and/or related demonstrable background
* Proven track record in delivering 1st time success with complex mixed signal IC’s.
* Metric driven verification - Verification planning, requirements extraction - Directed and constrained random verification - Functional and code coverage analysis.
* Formal Verification techniques.
* SystemVerilog - SVA (SystemVerilog Assertions)
* Testbench design with verification frameworks like UVM/OVM, e, VMM
* Object orientated programming (OOP) - Use of OOP design patterns
* Scripting experience with Ruby, sh/csh, TCL, Make, Perl
* Debugging skills - RTL - Testbench, OOP - Gate level (including SDF)
* Power aware verification (using CPF/UPF)
* Strong ability to interpret results and resolve problems
* Highly developed communication skills
* An innovative, creative, lateral thinking problem solver