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9 days ago
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Principal Design Engineer


Cirrus Logic
Location: Edinburgh
Job type: Permanent
Sector: Manufacturing
Category: Design / Development Jobs
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We have a fantastic opportunity for a Principal Design Engineer. You will have the opportunity to make big contribution in the areas of synthesis and timing constraints by working with the digital front-end and physical design teams to drive and refine the synthesis flow, constraints definition and timing sign-off across IP and chip level. This is a great opportunity to work with gifted engineers operating at the forefront of bleeding-edge technology! In return, we offer an incredible benefits package, along with a unique work culture that rivals no other.

Responsibilities

* Work with project leads to help develop signoff timing constraints on chips
* Work with digital IP team on constraints definition
* Some training and roll-out responsibility for digital project teams
* Work with physical design team to improve clock tree implementation
* Work with project teams to extract datasheet parameters from timing analysis
* RTL front-end design
* Develop custom constraints for power analysis modes
* Support power analysis debug with digital IP team, project leads and physical design engineers
* Block level synthesis flow development for IP design
* Analog timing model creation
* Formal verification

Required Skills and Qualifications

* Bachelor’s, Masters or Doctorate in Electrical Engineering or related discipline and relevant work experience
* Extensive knowledge of overall design flow RTL to GDS2
* RTL front-end design (need to be conversant and engaged in periodic design effort)
* Thorough understanding of ASIC timing
* Ability to apply that understanding to generating SDC constraints
* Ability to translate timing specs into SDC constraints
* Wide experience of industry standard EDA tools, particularly in RTL Synthesis, Static timing analysis, Digital power analysis and Formal verification
* Demonstrable experience of chip timing signoff
* Experience with scripting and flow automation
We have a fantastic opportunity for a Principal Design Engineer. You will have the opportunity to make big contribution in the areas of synthesis and timing constraints by working with the digital front-end and physical design teams to drive and refine the synthesis flow, constraints definition and timing sign-off across IP and chip level. This is a great opportunity to work with gifted engineers operating at the forefront of bleeding-edge technology! In return, we offer an incredible benefits package, along with a unique work culture that rivals no other.

Responsibilities

* Work with project leads to help develop signoff timing constraints on chips
* Work with digital IP team on constraints definition
* Some training and roll-out responsibility for digital project teams
* Work with physical design team to improve clock tree implementation
* Work with project teams to extract datasheet parameters from timing analysis
* RTL front-end design
* Develop custom constraints for power analysis modes
* Support power analysis debug with digital IP team, project leads and physical design engineers
* Block level synthesis flow development for IP design
* Analog timing model creation
* Formal verification

Required Skills and Qualifications

* Bachelor’s, Masters or Doctorate in Electrical Engineering or related discipline and relevant work experience
* Extensive knowledge of overall design flow RTL to GDS2
* RTL front-end design (need to be conversant and engaged in periodic design effort)
* Thorough understanding of ASIC timing
* Ability to apply that understanding to generating SDC constraints
* Ability to translate timing specs into SDC constraints
* Wide experience of industry standard EDA tools, particularly in RTL Synthesis, Static timing analysis, Digital power analysis and Formal verification
* Demonstrable experience of chip timing signoff
* Experience with scripting and flow automation
Apply

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